#Multiclock domain full#
#Multiclock domain tv#

4 Hardware design based on a digital signal processor, 5 application-specific integrated circuit (ASIC), 6, 7 or field-programmable gate array (FPGA) is more competent for real-time depth estimation implementation and design embedding than PC-based design. High definition is necessary to provide high image quality in this condition.ĭepth estimation has been thoroughly studied and a broad spectrum of approaches are summarized and compared by Scharstein and Szeliski.

So resolution reduction of each viewing zone is inevitable for multiview 3-D. The partial content of each view is synthesized into one image which includes eight or more views for autostereoscope display.

#Multiclock domain tv#

In 3-D TV and free-viewpoint TV (FTV) 2 applications, depth image based rendering (DIBR) 3 is used to generate the arbitrary virtual views. The results of depth estimation can also be used for driving assistance for automatic driving vehicles and robot navigation. The implementation can be included in the video systems for live 3-D television applications and can be used as an independent hardware module in low-power integrated applications.īy using dense depth information, three-dimensional (3-D) video systems 1 such as 3-D Blue-ray, 3-D television (TV) sets provide stereo video, which has multiple views for different viewers.

#Multiclock domain full#

The system performs with high efficiency and stability by using a full pipeline design, multiresolution processing, synchronizers which avoid clock domain crossing problems, efficient memory management, etc. The proposed field-programmable gate array (FPGA)-based architecture implements a fusion strategy matching algorithm for efficiency design. This paper presents a hardware implementation of a full high-definition (HD) depth estimation system that is capable of processing full HD resolution images with a maximum processing speed of 125 fps and a disparity search range of 240 pixels. Meanwhile, high-resolution depth maps are necessary to provide a good image quality on autostereoscopic displays which deliver stereo content without the need for 3-D glasses. The depth estimation algorithm is especially complex and it is an obstacle for real-time system implementation. 238000005070 sampling Methods 0.Three-dimensional (3-D) video brings people strong visual perspective experience, but also introduces large data and complexity processing problems.230000005540 biological transmission Effects 0.000 claims description 20.Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Application filed by ZTE Corp filed Critical ZTE Corp Priority to CNB2005100985606A priority Critical patent/CN100392560C/en Publication of CN1924758A publication Critical patent/CN1924758A/en Application granted granted Critical Publication of CN100392560C publication Critical patent/CN100392560C/en Status Expired - Fee Related legal-status Critical Current Anticipated expiration legal-status Critical Links Original Assignee ZTE Corp Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) ( en Inventor 林晓涛陈家锦汪坚 Current Assignee (The listed assignees may be inaccurate.

Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Granted Application number CN 200510098560 Other languages Chinese ( zh) Google Patents CN1924758A - Multi-clock domain system reset circuit CN1924758A - Multi-clock domain system reset circuit